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NBSG16VS 2.5V/3.3V SiGe Differential Receiver/Driver with Variable Output Swing
Description
1
QFN-16 MN SUFFIX CASE 485G
Features
* * * * * * * * * * *
Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 40 ps Typical Rise and Fall Times (VCTRL = VCC - 1 V) 120 ps Typical Propagation Delay (VCTRL = VCC - 1 V) Variable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Variable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V Output Level (100 mV to 750 mV Peak-to-Peak Output; VCC - VEE = 3.0 V to 3.465 V), Differential Output Only 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V EP Devices VBB and VMM Reference Voltage Output Pb-Free Packages are Available
A L Y W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
1
July, 2006 - Rev. 7
Publication Order Number: NBSG16VS/D
CC CC
The NBSG16VS is a differential receiver/driver targeted for high frequency applications that require variable output swing. The device is functionally equivalent to the EP16VS device with much higher bandwidth and lower EMI capabilities. This device may be used for applications driving VCSEL lasers. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The output amplitude is varied by applying a voltage to the VCTRL input pin. Outputs are variable swing ECL from 100 mV to 750 mV amplitude, optimized for operation from VCC - VEE = 3.0 V to 3.465 V. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For single-ended input operation, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open.
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SG 11 ALYW FCBGA-16 BA SUFFIX CASE 489
16
SG 16VS ALYWG G
NBSG16VS
1 A
VEE
2
NC
3
VCTRL
4
VEE
VEE 16 VTD
VBB VMM 15 14
VEE 13 Exposed Pad (EP)
1 2 NBSG16VS 3 4
12 11 10 9
VCC Q Q VCC
B
D
VTD
VCC
Q
D
Q
C
D
VTD
VCC
D VTD
D
VEE
VBB
VMM
VEE
5 VEE
6
7
8
NC VCTRL VEE
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin BGA C2 C1 QFN 1 2 Name VTD D I/O - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - - Description Internal 50 W Termination Pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
B1
3
D
Noninverted Differential Input. Internal 75 kW to VEE.
B2 A1,D1,A4, D4 A2 A3 B3,C3 B4 C4 D3 D2 N/A
4 5,8,13,16 6 7 9,12 10 11 14 15 -
VTD VEE NC VCTRL VCC Q Q VMM VBB EP
Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage No Connect Output Amplitude Swing Control. Bypass Pin to VCC through 0.1 mF Capacitor.
- RSECL Output RSECL Output - - -
Positive Supply Voltage Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V LVCMOS Reference Voltage Output. (VCC - VEE)/2 ECL Reference Voltage Output Exposed Pad. (Note 2)
1. The NC pin is electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.
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VCC + VCTRL 0.1 mF VCTRL VTD 50 W D D Q 50 W VTD 75 KW 75 KW VBB VCC - 2 V VEE VEE 50 W 50 W VTD VCC 36.5 KW Q Q OUT Q OUT VMM VTD 50 W D D 50 W 75 KW 75 KW Q 140 W VBB 140 W 36.5 KW Q Q OUT Q OUT VMM RVAR VCTRL VCC +3.3 V
Figure 3. Logic Diagram/ Voltage Source Implementation
Figure 4. Alternative Voltage Source Implementation
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL CONNECTIONS Connect VTD and VTD to VCC Connect VTD and VTD Together Bias VTD and VTD Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. VMM should be connected to the unused complementary differential input.
LVCMOS
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Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor (D, D) Internal Input Pullup Resistor (D) ESD Protection Moisture Sensitivity (Note 4) FCBGA-16 QFN-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Pb Pkg Level 3 Level 1 Value 75 kW 36.5 kW > 2 kV > 100 V Pb-Free Pkg N/A Level 1
UL 94 V-0 @ 0.125 in 192
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI VINPP IOUT IIN IBB IMM TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Output Current Input Current Through RT (50 W Resistor) VBB Sink/Source VMM Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 5) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 2S2P (Note 5) 2S2P (Note 6) 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN |D - D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w 2.8 V VCC - VEE t 2.8 V Continuous Surge Static Surge VI v VCC VI w VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC - VEE| 25 50 45 80 1 1 -40 to +85 -65 to +150 108 86 41.6 35.2 5.0 4.0 225 225 Unit V V V V V V mA mA mA mA mA mA C C C/W C/W C/W C/W C/W C/W C
qJC Tsol
Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. JEDEC standard 51-6 multilayer board - 2S2P (2 signal, 2 power). 6. JEDEC standards multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) (Max Swing) (VCTRL = VCC - 600 mV) VIH VIL VBB VIHCMR Input HIGH Voltage (Single-Ended) (Notes 10 and 11) Input LOW Voltage (Single-Ended) (Notes 10 and 12) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 9) (Differential Configuration) CMOS Output Voltage Reference (VCC - VEE)/2 Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) 645 1090 VTHR + 75 VIH - 2500 1080 1.2 765 1210 VCC - 1000* VCC - 1400* 1140 885 1330 VCC VTHR - 75 1200 2.5 605 1035 VTHR + 75 VIH - 2500 1080 1.2 725 1155 VCC - 1000* VCC - 1400* 1140 845 1275 VCC VTHR - 75 1200 2.5 600 1010 VTHR + 75 VIH - 2500 1080 1.2 720 1130 VCC - 1000* VCC - 1400* 1140 840 1250 VCC VTHR - 75 1200 2.5 mV mV mV V Min 18 1315 Typ 25 1440 Max 32 1565 Min 18 1305 25C Typ 25 1430 Max 32 1555 Min 18 1305 85C Typ 25 1430 Max 32 1555 Unit mA mV mV
VMM RTIN IIH IIL
mV 1100 45 1250 50 30 25 1400 55 100 50 1100 45 1250 50 30 25 1400 55 100 50 1100 45 1250 50 30 25 1400 55 100 50 W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 8. All loading with 50 W to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 11. VIH cannot exceed VCC. 12. VIL always w VEE.
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Table 6. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 18)
-40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) (Max Swing) (VCTRL = VCC - 600 mV) Input HIGH Voltage (Single-Ended) (Notes 15 and 16) Input LOW Voltage (Single-Ended) (Notes 15 and 17) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 14) (Differential Configuration) CMOS Output Voltage Reference (VCC - VEE)/2 Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 20 2095 1275 1750 VTHR + 75 VIH - 2500 1880 1.2 Typ 27 2220 1395 1870 VCC - 1000* VCC - 1400* 1940 Max 34 2345 1515 1990 VCC VTHR - 75 2000 3.3 Min 20 2085 1285 1730 VTHR + 75 VIH - 2500 1880 1.2 25C Typ 27 2210 1405 1850 VCC - 1000* VCC - 1400* 1940 Max 34 2335 1525 1970 VCC VTHR - 75 2000 3.3 Min 20 2075 1295 1715 VTHR + 75 VIH - 2500 1880 1.2 85C Typ 27 2200 1415 1835 VCC - 1000* VCC - 1400* 1940 Max 34 2325 1535 1955 VCC VTHR - 75 2000 3.3 mV mV mV V Unit mA mV mV
VIH VIL VBB VIHCMR
VMM RTIN IIH IIL
mV 1500 45 1650 50 30 25 1800 55 100 50 1500 45 1650 50 30 25 1800 55 100 50 1500 45 1650 50 30 25 1800 55 100 50 W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 13. All loading with 50 W to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 15. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 16. VIH cannot exceed VCC. 17. VIL always w VEE. 18. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V.
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Table 7. DC CHARACTERISTICS, NECL INPUT WITH VARIABLE NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 19) -40C Symbol IEE VOH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 20) -3.465 V v VEE v -3.0 V -3.0 V t VEE v -2.375 V Output LOW Voltage (Note 20) -3.465 V v VEE v -3.0 V (Max Swing) (VCTRL = VCC - 600 mV) -3.0 V t VEE v -2.375 V (Max Swing) (VCTRL = VCC - 600 mV) Input HIGH Voltage (Single-Ended) (Notes 22 and 23) Input LOW Voltage (Single-Ended) (Notes 22 and 24) NECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 21) (Differential Configuration) CMOS Output Voltage Reference (Note 25) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 20 -1205 -1185 Typ 27 -1080 -1060 Max 34 -955 -935 Min 20 -1215 -1195 25C Typ 27 -1090 -1070 Max 34 -965 -945 Min 20 -1225 -1195 85C Typ 27 -1100 -1070 Max 34 -975 -945 mV -2000 -1560 -1855 -1410 VTHR + 75 VIH - 2500 -1420 -1910 -1440 -1620 -1215 VCC - 1000* VCC - 1400* -1360 -1820 -1320 -1290 -1000 VCC VTHR - 75 -1300 0.0 -1990 -1580 -1895 -1460 VTHR + 75 VIH - 2500 -1420 -1900 -1460 -1705 -1290 VCC - 1000* VCC - 1400* -1360 -1810 -1340 -1425 -1100 VCC VTHR - 75 -1300 0.0 -1980 -1595 -1900 -1490 VTHR + 75 VIH - 2500 -1420 -1890 -1475 -1730 -1330 VCC - 1000* VCC - 1400* -1360 -1800 -1355 mV -1470 -1150 VCC VTHR - 75 -1300 0.0 mV mV mV V Unit mA mV
VOL
VIH VIL VBB VIHCMR
VEE+1.2
VEE+1.2
VEE+1.2
VMM RTIN IIH IIL
VMMT - 150 45
VMMT 50 30 25
VMMT + 150 55 100 50
VMMT - 150 45
VMMT 50 30 25
VMMT + 150 55 100 50
VMMT - 150 45
VMMT 50 30 25
VMMT + 150 55 100 50
mV W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 19. Input and output parameters vary 1:1 with VCC. 20. All loading with 50 W to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 21. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 22. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 23. VIH cannot exceed VCC. 24. VIL always w VEE. 25. VMM typical = |VCC-VEE| / 2 + VEE = VMMT.
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Table 8. AC CHARACTERISTICS for FCBGA-16 VCC = 0 V; VEE = -3.465 V to -3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 8) (Note 26) Propagation Delay to Output Differential (VCTRL = VCC - 2 V) D Q, Q (VCTRL = VCC - 1 V) D Q, Q Duty Cycle Skew (Note 27) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 28) Output Rise/Fall Times (20% - 80%) @ 1 GHz (VCTRL = VCC - 2 V) Q, Q (VCTRL = VCC - 1 V) Q, Q 75 0.8 TBD 2600 75 2 0.8 TBD 2600 75 2 0.8 TBD 2600 mV ps 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 2 Min 10.7 (Note 29) Typ 12 Max Min 10.7 (Note 29) 25C Typ 12 Max Min 10.7 (Note 29) 85C Typ 12 Max Unit GHz ps 100 100 125 120 3 145 140 10 100 100 125 120 3 145 140 10 100 100 125 120 3 145 140 10 ps ps
tSKEW tJITTER
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 26. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. Input edge rates 40 ps (20% - 80%). 27. tSKEW = |tPLH-tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 28. VINPP(MAX) cannot exceed VCC - VEE (applicable only when VCC - VEE t 2600 mV). 29. Conditions include input amplitude of 500 mV and VCTRL = VCC - 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P Spec in Figure 8).
Table 9. AC CHARACTERISTICS for FCBGA-16 VCC = 0 V; -3.0 V tVEE v -2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 9) (Note 30) Propagation Delay to Output Differential (VCTRL = VCC - 2 V) D Q, Q (VCTRL = VCC - 1 V) D Q, Q Duty Cycle Skew (Note 31) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 32) Output Rise/Fall Times (20% - 80%) @ 1 GHz (VCTRL = VCC - 2 V) Q, Q (VCTRL = VCC - 1 V) Q, Q 75 0.9 TBD 2600 75 3 0.9 TBD 2600 75 3 0.9 TBD 2600 mV ps 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 3 Min 10.7 (Note 33) Typ 12 Max Min 10.7 (Note 33) 25C Typ 12 Max Min 10.7 (Note 33) 85C Typ 12 Max Unit GHz ps 100 100 125 120 3 145 140 10 100 100 125 120 3 145 140 10 100 100 125 120 3 145 140 10 ps ps
tSKEW tJITTER
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 30. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. Input edge rates 40 ps (20% - 80%). 31. tSKEW = |tPLH-tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 32. VINPP(MAX) cannot exceed VCC - VEE (applicable only when VCC - VEE t 2600 mV). 33. Conditions include input amplitude of 500 mV and VCTRL = VCC - 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P Spec in Figure 9).
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Table 10. AC CHARACTERISTICS for QFN-16 VCC = 0 V; VEE = -3.465 V to -3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 8) (Note 34) Propagation Delay to Output Differential (VCTRL = VCC - 2 V) D Q, Q (VCTRL = VCC - 1 V) D Q, Q Duty Cycle Skew (Note 35) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 36) Output Rise/Fall Times (20% - 80%) @ 1 GHz (VCTRL = VCC - 2 V) Q, Q (VCTRL = VCC - 1 V) Q, Q 75 0.5 TBD 2600 75 2 0.5 TBD 2600 75 2 0.5 TBD 2600 mV ps 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 2 Min 10 (Note 37) Typ 12 Max Min 10 (Note 37) 25C Typ 12 Max Min 10 (Note 37) 85C Typ 12 Max Unit GHz ps 100 100 140 135 3 180 180 20 100 100 140 135 3 180 180 15 100 80 140 135 3 180 220 10 ps ps
tSKEW tJITTER
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 34. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. Input edge rates 40 ps (20% - 80%). 35. tSKEW = |tPLH-tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 36. VINPP(MAX) cannot exceed VCC - VEE (applicable only when VCC - VEE t 2600 mV). 37. Conditions include input amplitude of 500 mV and VCTRL = VCC - 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P Spec in Figure 8).
Table 11. AC CHARACTERISTICS for QFN-16 VCC = 0 V; -3.0 V tVEE v -2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 9) (Note 38) Propagation Delay to Output Differential (VCTRL = VCC - 2 V) D Q, Q (VCTRL = VCC - 1 V) D Q, Q Duty Cycle Skew (Note 39) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 40) Output Rise/Fall Times (20% - 80%) @ 1 GHz (VCTRL = VCC - 2 V) Q, Q (VCTRL = VCC - 1 V) Q, Q 75 0.5 TBD 2600 75 3 0.5 TBD 2600 75 3 0.5 TBD 2600 mV ps 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 3 Min 10 (Note 41) Typ 12 Max Min 10 (Note 41) 25C Typ 12 Max Min 10 (Note 41) 85C Typ 12 Max Unit GHz ps 100 100 140 135 3 180 180 20 100 100 140 135 3 180 180 15 80 100 140 135 3 180 220 10 ps ps
tSKEW tJITTER
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 38. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. Input edge rates 40 ps (20% - 80%). 39. tSKEW = |tPLH-tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 40. VINPP(MAX) cannot exceed VCC - VEE (applicable only when VCC - VEE t 2600 mV). 41. Conditions include input amplitude of 500 mV and VCTRL = VCC - 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P Spec in Figure 9).
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100 90 OUTPUT AMPLITUDE (%) 80 70 60 50 40 30 20 10 0 VCC - 0.0 VCC - 0.5 VCC - 1.0 VCTRL (V) VCC - 1.5 VCC - 2.0
Figure 5. Output Amplitude % vs. VCTRL (pin #A3)
VOH MIN. AMPLITUDE REGION OUTPUT AMPLITUDE AMPLITUDE DECREASES MAX. AMPLITUDE REGION VOL 2.375 V v VCC - VEE < 3.0 V
3.0 V v VCC - VEE v 3.465 V VCC - 1.3 VCC - 0.0 VCC - 0.5 VCC - 1.0 VCTRL (V) VCC - 1.5 VCC - 2.0
Figure 6. Output Amplitude vs. VCTRL (pin #A3)
3.40 3.20 3.00 VOLTAGE (V) 2.80 2.60 2.40 2.20 2.00 1.80 1.60 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20 Q/Q VCTRL
Figure 7. Output Response Under Amplitude Modulation of VCTRL (Conditions Include VCC - VEE = 3.3 V at 255C, fIN (VCTRL) = 200 MHz, and fIN (D, D) = 2 GHz)
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900 OUTPUT VOLTAGE AMPLITUDE (mV) 800 VCTRL = VCC - 2 V JITTEROUT ps (RMS) 9 VCTRL = VCC - 2 V 8 JITTEROUT ps (RMS) 7 VCTRL = VCC - 1 V 500 400 300 200 100 RMS JITTER 0 1 2 3 4 5 6 7 8 9 10 11 12 OUTPUT P-P SPEC (AMPLITUDE GUARANTEE) VCTRL = VCC - 0 V 4 3 2 1 0 6 5 700 600 500 400 300 200 100 RMS JITTER 0 1 2 3 4 5 6 7 8 9 10 11 12 0 OUTPUT P-P SPEC (AMPLITUDE GUARANTEE) VCTRL = VCC - 0 V VCTRL = VCC - 1 V 7 6 5 4 3 2 1 9 8
INPUT FREQUENCY (GHz)
Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
800 OUTPUT VOLTAGE AMPLITUDE (mV) 700 600
INPUT FREQUENCY (GHz)
Figure 9. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 10. AC Reference Measurement
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Zo = 50 W
Q Driver Device Q
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NBSG16VSBA NBSG16VSBAR2 NBSG16VSMN NBSG16VSMNG NBSG16VSMNR2 NBSG16VSMNR2G Package FCBGA-16 FCBGA-16 QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 100 Units / Tray (Contact Sales Representative) 100 / Tape & Reel 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel
Board NBSG16VSBAEVB
Description NBSG16VSBA Evaluation Board
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
FCBGA-16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O
-X- D M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC
-Y- K E
M 0.20
3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D
e
4
3
2
1
3
16 X
b 0.15 0.08
M M
S VIEW M-M
ZXY Z
5 0.15 Z A A2 -Z-
A1
16 X
4 DETAIL K
0.10 Z
ROTATED 90 _ CLOCKWISE
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13
NBSG16VS
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50
D
A B
PIN 1 LOCATION
0.15 C 0.15 C 0.10 C TOP VIEW
16 X
0.08 C SIDE VIEW A1 C
16X
L
5
NOTE 5 4
16X
K
1 12
16X
b BOTTOM VIEW 0.50 0.02
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
CC CC
(A3) D2 e
8 9 16 13
E
A
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
0.575 0.022
EXPOSED PAD
EXPOSED PAD
E2 e
3.25 0.128
1.50 0.059
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and solderin details, please download the ON Semiconductor Soldering an Mounting Techniques Reference Manual, SOLDERRM/D.
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14
NBSG16VS/D

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